The present invention relates to a DC-DC converter in a current-mode control system which has a synchronization function to external clock.
In recent years, switching-type DC-DC converters have been used frequently in power supply circuits for supplying power source voltages to electronic circuits in various electronic equipment represented by mobile equipment. As energy saving and multiple functions have been increasingly required of the equipment, these power supply circuits have been requested to have a synchronous operation function when a plurality of DC-DC converters are provided in combination or respond at a higher speed during a transient time such as a sudden load change. To respond to the requests, a DC-DC converter in a current-mode control system which is excellent in high-speed responsivity has been used.
Referring to FIGS. 6A and 6B, a DC-DC converter in a current-mode control system will be described herein below.
A description will be given first to a typical circuit structure of the DC-DC converter in the current mode control system with reference to FIG. 6A.
As shown in FIG. 6A, a high-side switch 11 and a low-side switch 12 are connected in series and an input voltage Vin is applied thereto. The high-side switch 11 and the low-side switch 12 are alternately turned ON/OFF so that a switching voltage is generated at a connection point between the high-side and low-side switches 11 and 12.
An inductor 13 and a capacitor 14, which are connected to the connection point between the high-side and low-side switches 11 and 12, constitute an LC filter. The LC filter rectifies and smoothes the switching voltage generated at the connection point between the high-side and low-side switches 11 and 12 and generates an output voltage Vout.
An error amplifier 15 compares the output voltage Vout with a reference voltage Vref, amplifies the result of the comparison, and outputs an error signal Ve. A lamp signal generating circuit 16 outputs a lamp signal Vc having a sawtooth waveform and synchronous with a clock signal CLK. An arithmetic operation circuit 17 subtracts the lamp signal Vc from the error signal Ve and produces an output signal (Ve−Vc). A current detecting circuit 18 detects a current flowing in the inductor 13 and outputs a current signal Vi. A comparator 19 compares the output signal (Ve−Vc) from the arithmetic operation circuit 17 with the current signal Vi and outputs the result of the comparison.
An RS latch 20 is set by the clock signal CLK, reset based on the output signal (Ve−Vc) from the comparator 19, and outputs a drive signal to each of the high-side and low-side switches 11 and 12.
A description will be given next to the operation of a typical DC-DC converter in a current-mode control system.
First, when the RS latch 20 is set by the clock signal CLK, the high-side switch 11 is turned ON, while the low-side switch 12 is turned OFF. At this time, a differential voltage (Vin−Vout) between the input voltage Vin and the output voltage Vout is applied to the inductor 13. Since the inductor 13 is magnetized by the differential voltage (Vin−Vout), a current flowing in the inductor 13 increases. Accordingly, the current signal Vi relative to the current flowing in the inductor 13 also increases. On the other hand, the lamp signal generating circuit 16 gradually increases the lamp signal Vc from zero so that the output signal (Ve−Vc) as the result of the arithmetic operation between the error signal Ve and the lamp signal Vc in the arithmetic operation circuit 17 gradually decreases. When the level of the current signal Vi exceeds that of the output signal (Ve−Vc), the output signal from the comparator 19 is inverted so that the RS latch 20 is reset by the inverted output signal. This turns OFF the high-side switch 11 and turns ON the low-side switch 12.
When the high-side switch 11 is in the OFF state and the low-side switch 12 is in the ON state, the output voltage Vout is reversely applied to the inductor 13. As a result, the inductor 13 is demagnetized by a voltage (−Vout) so that the current flowing in the inductor 13 decreases. The resulting state continues till the RS latch 20 is set again by the clock signal CLK to turn ON the high-side switch 11 and turn OFF the low-side switch 12. An output voltage Vout is supplied by repeating the foregoing operation.
A description will be given next to the operation of stabilizing the output voltage Vout.
When the output voltage Vout shows a tendency to exceed a desired value, the error amplifier 15 lowers the error signal Ve. Accordingly, the level difference by which the current signal Vi is higher than the output signal (Ve−Vc) from the arithmetic operation circuit 17 also decreases to consequently reduce the current flowing in the inductor 13. In other words, the suppression of power supplied to the output eventually lowers the output voltage Vout. Conversely, when the output voltage Vout lowers, an operation opposite to the operation described above is performed to raise the output voltage Vout.
FIG. 6B shows the respective operation waveforms of the clock signal CLK, the lamp signal Vc, the output signal (Ve−Vc) from the arithmetic operation circuit 17, and the current signal Vi.
There has been known a phenomenon in which such a control operation becomes unstable when the ON time of the high-side switch 11 accounts for 50% or more of the switching period in the absence of the lamp signal Vc from the lamp signal generating circuit 16. To improve the phenomenon of such an unstable control operation, a technology termed slope compensation has been proposed which superimposes the lamp signal Vc on the error signal Ve with which the current signal Vi is compared. With regards to the slope compensation, a technology which sets the slope of the lamp signal from the output voltage is disclosed in, e.g., Patent Document 1, while a technology which sets the slope of the lamp signal from the input/output voltages has been disclosed in Patent Document 2.